As the size of semiconductor devices decreases, the density of semiconductor devices increases, and the interconnect density within substrates and printed circuit board (“PCB”) increases. To provide such increased interconnections, the interconnect dimensions and spacing decrease, and the number of interconnect layers increase. Multiple interconnect layers may be fabricated so that conductive layers are separated by dielectric layers. A via in a semiconductor substrate or PCB provides an electrical connection between conductors on different layers of the substrate or PCB. For example, a via may provide an electrical connection from the surface of the substrate or PCB to a conductive trace within the substrate or PCB.
Via technology has proven to pose major challenges to package reliability. One of the most prevalent issues surrounding via formation is via delamination, a defect commonly characterized by the separation of the via from the underlying metal. Via delamination typically manifests itself as opens or as high resistance failures during electrical continuity testing. In particular, package microvia integrity is a critical concern during process ramps and for high process manufacturing purposes. Via delamination is currently a significant reliability issue affecting downstream users. Delamination may result in “NO BOOT” fails at the test process level, currently manifesting at greater than ten thousand defects per million, delaying production and driving up costs.
According to the current state of the art, as seen for example in FIG. 1A, a package substrate 100 includes a core 110, such as, for example, a silicon core, conductive layers 120, 120′, 120″ and 120′″, and a dielectric material 130 separating the conductive layers. A plated through hole 112 includes supporting core 113 therein, made, for example, of an epoxy resin, the supporting core being plated with a conductive material 114, such as, for example, copper. The conductive layers 120, 120′, 120″ and 120′″ may further comprise copper. As further seen in FIG. 1, the shown configuration includes conductive layers 120 and 120′″ which each include an electrolessly plated first layer 125, such as a player of elecrolessly plated copper, and an electrolytically plated second layer 126 such as an electrolytically plated copper. The dielectric material 130 insulates the conductive layers from each other. Via 140 provides electrical connections between conductive layers 120 and 120′ separated by dielectric material 130. The via is meant to extend through the dielectric material 130 to allow electrical contact between different conductive layers 120. As seen in FIG. 1, the provision of vias on a package level typically involves top and bottom processing, as seen for example by the presence of vias 140 and 140′. Various factors, such as, for example, thermal expansion of the dielectric material 130, can produce a vertical tensile stresses on vias, such as via 140, which can cause the bottom of the via to detach from bottom conductive layer 120′, creating a delamination void. The existence of a delamination void means that via 140 cannot effectively provide an electrical connection between conductive layer 120 and 120′.
Referring next to FIG. 2A, an optical image of a staggered via is provided. FIG. 2B shows a detail of FIG. 2B depicting a failing via, the delamination at 150 being visible at the bottom of the via.
The problem of via delamination is exacerbated in the case of a via-on-via, or stacked via configuration, as seen for example in FIG. 3. A series 1000 of stacked vias 1400 and 1410 are shown with the bottom via 1410 as having failed through delamination at 1500. Stacked via configurations typically result in higher rates of delamination by virtue of the higher stresses inherent in the package structural design. Typically, the risk of incurring defects in stacked via configurations is mitigated by the use of improved dielectric materials that are less prone to thermal expansion or by lessening the number of vias that are stacked above one another. However, future technologies will tend to rely further on larger numbers of stacked vias as well as on smaller via dimensions.
The state of the art currently attempts to address the problem of via delamination in general in a number of ways, such as, for example, through optimization of the substrate manufacturing process and through implementation of tighter process controls; through the use of dielectric materials less prone to tensile stresses as a result of temperature shifts; through the creation of redundant vias, particularly in areas that are prone to failure such as areas of high mechanical stress; and through an increase the size of vias. In addition, a number of added process steps are typically implemented in order to monitor defects caused by via delamination. For example, a process referred to as “Temp Shock ‘C’” monitoring may be implemented in order to monitor via delamination by subjecting units to be tested to large temperature gradients in order to accelerate failure. Additionally, in a process referred to as “R-shift nets” coverage, a continuity test from device pin to bumps, provides for the testing of pre-selected vias by measuring their resistance. To control problems associated with via delamination, the state of the art increases R-shift nets processing by increasing the number of vias tested in order to monitor unit failures.
Interlocking via formation has been used on the wafer level in prior generation silicon processes with a conventional backend interconnect scheme (that is, on a single side of the wafer) in order to improve robustness against via delamination. On the wafer level, vias were formed with an anchor like structure at their bottom regions which held the vias under the wafer insulator. U.S. Pat. No. 5,619,071 relates to the provision of interlocking vias at the wafer level.
The state of the art fails to provide a reliable method of containing via delamination for improving package via integrity.